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Certified VLSI Design Engineer

NQR Code:2022/EHW/NIELIT/06345

  • Old Code: 2022/EHW/NIELIT/06345

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About this Qualification

Job Description

● Designing of VLSI circuits ● Designing of Embedded Systems ● Fault & Error identification in Digital Circuits

Progression Pathway

  • Academic: This course is frequently updated in synchronization with the industry to provide the trainees in-depth knowledge and skills required by Embedded & VLSI markets around the globe. It provides comprehensive understanding about the fundamental principles
  • methodologies and industry practices. Professional: This uniquely hybrid course makes the successful participants readily employable in multiple roles available in broad spectrum of relevant industries like: (a) Circuit Layout Designing (b) Circuit Testing Research and Development: For people interested in entrepreneurships this would be an excellent launch pad. In addition
  • the course also serves as a concrete platform for people involved in application research
  • consultancy and high-end product development in both industry and academia.

Learning Module In Job Role/Qualifcation

National Occupation Standards (NOS)/Module NOS Code Mandatory/ Optional Estimated size (Hours) Nos Credit Level
INTRODUCTION TO DIGITAL ELECTRONICS ● Introduction to Number Systems, Logic Gates ● Understanding Combinational Logic Circuit Designing -Adder, Subtractor, MUX, DEMUX, Encoder and Decoder etc. ● Understanding Sequential Logic Circuit Designing-Latches, F N.A. 35 N.A. 5
INTRODUCTION TO VLSI ● Need, Scope, Use and History of VLSI ● Introduction to Chip Design Process ● Description of Hardware Description Languages ● Applications of VLSI ● VLSI Design Flow ● Moore’s Laws ● VLSI Design Flow and Y-Chart ● Front-Back End VL N.A. 35 N.A. 5
VERILOG HDL ● Overview of Digital Design with Verilog HDL ● Evolution of CAD ● Emergence of HDLs, typical HDL-based design flow ● Why Verilog HDL, trends in HDLs. ● Hierarchical Modeling Concepts ● Top-down and bottom-up design methodology ● Difference N.A. 50 N.A. 5
MODELING TECHNIQUES ● Gate-Level Modeling ● Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise ● Fall and tum-off delays, min, max, and typical delays. Dataflow Modeling ● Continuous assignments ● Delay sp N.A. 70 N.A. 5
FPGA ARCHITECTURE AND PROTOTYPING ● Introduction to FPGA, Architecture ● Internal resource and Design Essentials ● FPGA Input/output Blocks (IOBs), Special FPGA functions ● Logic Synthesis, FPGA Programming with Verilog basics, Tool Training ● Different N.A. 50 N.A. 5
INTRODUCTION TO THE MOS TECHNOLOGY ● Introduction to IC technology MOS, PMOS, NMOS, CMOS & BiCMOS Technologies ● Basic Electrical Properties of MOS and BiCMOS Circuits ● IDS - VDS relationships ● MOS transistor Threshold Voltage ● Figure of merit, Tran N.A. 50 N.A. 5
VLSI CIRCUIT DESIGN PROCESSES ● VLSI Design Flow ● MOS Layers ● Stick Diagrams, Design Rules and Layout ● Lambda(λ)-based design rules for wires, contacts and Transistors ● Layout Diagrams for NMOS and CMOS Inverters and Gates ● Scaling of MOS circuits, N.A. 70 N.A. 5
DESIGN VERIFICATION UVM, OVM AND AVM METHODOLOGY ● Introduction UVM, UVM Object ● UVM test Bench etc. ● Introduction OVM, OVM Reporting ● OVM Transaction ● OVM Configuration etc. ● Need for File Inter Change ● GDS2 Stream, Caltech Intermediate Format (C N.A. 60 N.A. 5
Sub-Total N.A. 420 N.A.
Employability Skills ● Introduction to Employability Skills ● Career Development & Goal Setting ● Becoming a Professional in the 21st Century ● Basic English Skills ● Communication Skills ● Financial and Legal Literacy ● Entrepreneurship ● Diversity N.A. 30 N.A.
On Job Training N.A. 30 N.A.
Total N.A. 480 N.A.